The present invention relates to photosensitive chips for creating electrical signals from an original image, as would be found, for example, in a digital scanner or facsimile machine. Specifically, the present invention relates to a guardring which is particularly useful in CMOS-based photosensor chips.
In the context of document processing, a raster input scanner, or simply xe2x80x9cscanner,xe2x80x9d is a device by which an image on a hard-copy original, such as a sheet of paper, is converted into digital data. A common design for a scanner includes a linear array of photosensitive elements, which form photosensors. Each photosensor in the array is adapted to output a signal, typically in the form of an electrical charge or voltage, of a magnitude proportional to or otherwise related to the intensity of light incident on the photosensor. By providing a linear array of these photosensors and causing the array to scan relative to the hard-copy original, each photosensor will output a sequence of charge signals resulting from the various gradations of dark and light in the image as the individual photosensors move through a path relative to the image.
In most low-cost scanners, such as presently found in inexpensive facsimile machines, the most typical technology for creating such a scanner is the charge-coupled device, or CCD. For higher-quality applications, an emergent technology is CMOS. Various patents related to using CMOS technology in a photosensor chip, such as used in a scanner, are assigned to the assignee hereof.
The number of photosensors that can be packed onto a single chip or wafer is limited, and this, in turn, limits the image resolution that can be achieved with a single photosensor array. Joining several of the smaller photosensor arrays together to form a longer array, and particularly, to form a full page width array with increased resolution along with the attendant simplification of the scanning system that this allows is desirable.
Photosensor arrays are formed from a plurality of generally rectangular substrates and are separated by sawing or other suitable means from one or more circular silicon wafers. Photosensor arrays may be assembled in the staggered relationship or butted end to end. If the arrays are placed end to end in a colinear fashion, the photodiodes and active circuitry needs to very close to the diced edge of the chip to prevent image quality problems.
One method presently employed to produce such photosensor arrays is the formation of aligned V-grooves in the wafer containing the semiconductive crystals so that after further processing the semiconductive crystals can be separated by dicing the wafer along the V-grooves. The V-grooves are structures that are etched along the 111 plane of the silicon, which is the easy slip plane for stress relief or cracks.
V-grooves are needed for proper dicing of the chips in regions very close to active circuits. If the V-groove is not there for each chip during dicing, chipping damage may occur and this will cause either a time xe2x80x9c0xe2x80x9d yield problem (meaning that a whole batch of fabricated diced wafers will be bad) or a reliability degradation problem in the final photosensor array. For more details, see U.S. Pat. Nos. 4,814,296 and 5,219,796 which are hereby incorporated by reference.
V-grooves are inspected in five locations on the wafer after processing. If the process is uniform across the wafer, these sample points are generally adequate. However, quite often the V-groove is not opened at all or is incomplete in random locations across the wafer, or in certain areas not covered by the sample locations. Only 100% visual inspection of all wafers catches all of these defects, or 100% inspection of a sample of wafers might indicate that there is a problem. Visual inspection of every chip on every wafer is labor intensive and prone to human error.
Briefly, the present invention obviates the problems noted above by utilizing a method for Fabrication of a Silicon photosensor Array on a wafer and testing the same. The invention allows checking of every V-groove on every chip. An implanted or diffused region is placed across the V-groove, with electrical connections on both ends of the diffusion. If the V-groove is formed the diffused region will be broken and the electrical path will be open. A deeper diffusion can be also used to check for incomplete V-grooves. If one end of the electrical path is tied to an existing I/O pad on the chip and the other end to the ground, this path will have no effect on the input resistance if the V-groove is formed. There will be a small, but acceptable, increase in input capacitance. If the V-groove is not formed, the connection will appear as a short or high leakage on the chip input, which will fail the DC test on that I/O. Thus, existing DC tests can be used to check normal I/O integrity and V-groove process completion.
There is provided a method for determining a condition of a V-groove on a wafer having a circuit structure thereon before the wafer is processed, cut and assembled, comprising the steps of: defining a V-groove region along the wafer; fabricating a circuit structure on the wafer; applying a test resistor along the V-groove region during said fabricating step; measuring a resistance value of said resistor after said fabricating step; comparing said resistance value to a predefined value to determine the condition of said V-groove.